Device and method for analyzing embedded systems

ABSTRACT

The invention discloses an analysis device for an embedded system ( 9 ) comprising a CPU ( 1 ), a CPU bus ( 2 ) and a memory ( 3 ). The embedded system has at least one communication module ( 4 ) for the input or output of analysis data by way of a test interface ( 5 ). The communication module permits the internal memory and the input and output access operations of the embedded system to be monitored and/or logged without using the clock cycles of the CPU ( 1 ).

BACKGROUND OF THE INVENTION

The present invention relates to an analysis device for an embeddedsystem, and a method for the analysis of an embedded system with ananalysis device.

To successfully develop software for embedded systems, it is a generalpractice to provide devices enabling error detection during theoperation time (debugging). In the known concept of debugging embeddedsystems by way of a so-called JTAG interface (Joint Test Action Group,IEEE Standard 1149.1-1990, ‘IEEE Standard Test Access Port and BoundaryScan Architecture’, Institute of Electrical and Electronics EngineersInc., New York, USA, 1990) it is possible to perform testing operationsby means of a ‘Boundary-Scan’ testing method. This method allowssingle-step processing of the processor (single stepping), the settingof break points (break points) and the setting of so-called watchpoints. Although these per se known auxiliary means for error detectionpermit monitoring the principal program execution and the condition ofvalues of single variables, generally the running system must be stoppedto this end. It is disadvantageous, however, that the output of themicrocomputer can no longer be in real time.

The problem encountered is that embedded systems frequently are realtime systems and, due to their typical range of application in real-timecontrols, do not allow being stopped for debugging purposes, not atleast for checking the data changed in connection with the real timeprocessing.

The so-called trace-interface is further known in the art, where theconduction of all relevant CPU bus signals (address signals, datasignals and control signals) by way of housing pins e.g. to an externallogic analysis device is enabled by using a ‘bond-out’ chip for the realtime analysis. The bond-out chip is a microcontroller (MCU) in anothercasing, where the processor bus (data, address and control signals) isbonded towards the outside.

With the high system frequencies of several hundred megahertz beingconventional nowadays for embedded systems and the modern memoryarchitectures with caches, this method for the error analysis can nolonger be used due to the high speed requirements. A real time output ofrelatively comprehensive data memories (for example, of a size of morethan 100 kilobyte) is generally impossible due to the system frequenciespredetermined on account of the technology employed and the resultingband width. One given possibility of creating the band width necessaryfor the real time data transfer would be a parallel output of the datato be transferred. However, the number of pins available for thispurpose is normally limited, not least for cost reasons.

In view of the above, an object of the invention is to provide ananalysis device for embedded systems, which can be employed also in theup-to-date quick embedded systems.

SUMMARY OF THE INVENTION

This object is achieved by an analysis having a CPU, a CPU bas, a memoryand a communication module.

The invention is based on the following reflections: On the one hand,the internal system condition of an embedded system can be described oranalyzed, respectively, by way of its present data memory contents(RAM). From this follows that in case this memory content can be copiedin real time into an external data memory, there is a possibility offurther processing and evaluating the system condition from this pointby means of a subsequent evaluation unit.

In the analysis device a copy of the internal system condition ispreferably written in real time into an external memory.

The analysis device is preferably part of an embedded system, which isemployed in particular in electronic control devices for motor vehiclebrake systems. In the embedded system according to the invention,preferably basic components of the system such as one or more CPUs andmemories are designed partly or fully redundantly. The safety ofoperation of the embedded system is hereby enhanced.

Preferably, the logging of data does not take place in such a fashionthat the entire memory content or the content of a whole memory range istransmitted. Rather, only the changes in the memory, especially allwrite access operations of the CPU and/or the periphery are transmitted.A reduction of the necessary band width for the data output can takeplace this way.

Further, the system preferably comprises a means for the direct dataoutput by the CPU. Apart from this means for the direct data output,especially a means for an automatic replication of the data in thebackground by way of the analysis module is provided. The result is theadvantage of an increased flexibility in the data output.

Especially for these cases of application, the invention discloses auniversal data input and output module configured in such a manner thatin real time a data exchange can be carried out by means of an embeddedsystem without having to stop (not even temporarily) this system(non-intrusive).

Compared to the software debugging devices known from the state of theart, the analysis device of the invention is advantageous in that in thedevelopment of control algorithms, e.g. for motor vehicle brake systems,the dynamic system behavior, especially the control variables, can bemonitored during the debugging operation. It is furthermore favorablethat a data input into the embedded system can be carried out for theemployment of an embedded system in a hardware-in-the-loop simulator orin a rapid-prototyping system.

Another objective of the invention is a method for the analysis of anembedded system as described hereinabove with an analysis device havinga CPU, a CPU bus, a memory and a communication module.

The method is advantageous in that the processing speed of the embeddedsystem is not reduced on account of the debugging processes running inthe background. This condition renders possible a real time processingof the data even during the debugging operation.

Preferably, the method of the invention also comprises steps for theoutput of the complete data memory contents in real time.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 illustrates an analysis device.

DETAILED DESCRIPTION OF THE DRAWING

The analysis device of the invention and the method of the inventionwill be described in the following by way of embodiments while makingreference to FIG. 1.

FIG. 1 shows an embedded system 9 with an analysis device 4 according tothe invention.

The embedded system 9 comprises one or more CPUs 1, one RAM 3, ananalysis device 4 and a debugging interface 5. To simplify the wiringdiagram, further conventional functional elements of the embedded systemsuch as ROM, clock generation, IO, etc., are not illustrated.

The analysis device includes three function modes that will be describedhereinbelow. In function mode 1 the analysis device reads for controlall write access operations of the CPU 1 to the data memory 3. Thismeans all write access operations of the CPU 1 to the data memory 3 arewritten automatically by way of CPU bus 2 by the suggested extended dataoutput/input unit 4 (EDP, Enhanced Data Port) by means of a controllercontained therein by way of a parallel interface 5 to the external datamemory 6. To this end, the controller must have at least the same bandwidth as the memory 3 used. Beside a connection to the data bus, thecontroller has in particular a connection to the control bus and to theaddress but in order that, according to a preferred embodiment of themethod, only especially selected address ranges and/or especiallyselected data types can be monitored for the analysis. Accordingly, CPU1 does not have to execute additional commands for tapping the data andfor the data transfer.

The external data memory 6 is preferably designed as a dual-port memoryand usually contains an exact reproduction of the memory rangesmonitored in RAM 3 or the entire memory content of RAM 3, respectively.Memory 6 can also be a magnetic core memory storing the arriving dataflow for a later (offline) analysis.

External interface 5 preferably has a band width that is smaller thanthe band width of the CPU bus. FIFO memory 8, which is arranged withinthe data output unit 4, ensures a time buffer of the tapped data. It isthis way possible to output also accesses to interface 5 where a cacheline or a CPU register dump is re-written upon entry into the function.

In the function mode 2 the analysis device 4 reads for control allreading access operations of CPU 1 to the data memory. This mode largelycorresponds to function mode 1, however, there are the followingdifferences: all reading access operations are automatically output byway of interface 5. Analysis unit 4 then registers all operations suchas read cycles, write cycles, etc., which are visible on the CPU bus(read for control). In function mode 2 CPU 1 actively performs a memorydump entailing, however, an insignificant tolerable loss in runningtime. Due to the analysis unit 4 reading for control, the number ofclock cycles necessary for the output of data words for the analysis arereduced or even avoided, respectively.

CPU 1 reads the data memory content into the registers (not shown) ofthe CPU. The data available in the registers can then be written inanalysis unit 4. The mode of function described herein basicallycorresponds to the function mode 3 that will be described hereinbelow.

In the analysis device suggested in the present example (function mode2), CPU 1 reads the data memory content into the CPU registers. Inparallel to this, the data output unit 4, which overhears the data bus,automatically outputs the corresponding data, i.e., there is no need foran explicit write cycle for the data output for the analysis.

In function mode 3 there is direct writing on the data output unit ordirect reading from the data output unit. Thus, function mode 3corresponds to function mode 1, apart from the fact that data isactively output by the CPU 1 externally to the analysis unit 4, or isread in actively from there, respectively, with the result, however,that additional clock cycles are necessary.

By way of module 7, the analysis unit can transfer data from theexternal memory 6 to typical debugging applications such as real-timemonitoring of the system condition 10, offline analysis for creating acomplete data memory reproduction by way of module 11, flash download byway of communication channel 12 (programming of the program memory),parameter variation during the operation of the embedded system,transfer of system stimuli, rapid prototyping and hardware-in-the-loopsimulation.

1-20. (canceled)
 21. An analysis device for an embedded systemcomprising: a CPU; a CPU bus; a memory (3); and at least onecommunication module for input or output of analysis data by way of atest interface, wherein the communication module permits the memory andinput and output access operations of the embedded system to bemonitored and/or logged without using clock cycles of the CPU.
 22. Theanalysis device of claim 21, wherein at least three freely selectableanalysis modes, with the analysis modes, in the way and extent ofparticipation of the CPU, differing from each other in the read and/orwrite operations of data for analyzing purposes.
 23. The analysis deviceof claim 22, wherein depending on the selected analysis mode, either allwrite access operations of the CPU are logged to especially definableaddress ranges without using clock cycles, or all read access operationsof the CPU are logged, or direct reading and writing of the CPU outof/into an external memory is executed by using clock cycles.
 24. Theanalysis device of claim 23, wherein the communication module comprisesa controller which, by way of a connection to at least a data bus, acontrol bus, or an address bus, can independently make access to the busof the embedded system in order to monitor write and/or read accessoperations in real time, without influencing of the CPU.
 25. Theanalysis device of claim 24, wherein the communication module isconnected to a buffer store and the data transferred in write and/orread access operations can be stored in the buffer store.
 26. Theanalysis device of claim 25, wherein the data can be output from thebuffer store in a buffered fashion by way of the test interface or datacan be read into the buffer store by way of the test interface.
 27. Theanalysis device of claim 23, wherein the external memory is a magneticcore memory or a dual-port memory.
 28. The analysis device of claim 21,wherein the communication module is integrated into the embedded system.29. The analysis device of claim 21, wherein the test interface isconnected to a test code memory arranged outside the embedded system.30. The analysis device of claim 21, wherein the data transfer from thecommunication module to an external memory takes place by way of aparallel interface.
 31. The analysis device of claim 30, wherein theexternal memory is connected to a data conditioning device providing aninterface connection to external debugging applications.
 32. An embeddedsystem comprising and analysis device, the embedded system comprising: acentral processor unit; a CPU bus; a memory; and at least onecommunication module for input or output of analysis data by way of atest interface, wherein the communication module permits the memory andinput and output access operations of the embedded system to bemonitored and/or logged without using clock cycles of the CPU.
 33. Amethod for analyzing an embedded system comprising: providing a centralprocessor unit; providing a CPU bus; providing a memory; providing atleast one communication module having at least input element and atleast one output element; providing at least one mode for analyzing datain real time without requiring the system to be stopped or interrupted,respectively, for the analysis.
 34. The method of claim 33, wherein thememory content or a correspondingly assessable information of theembedded system, in whole or in part, is copied in real time into anexternal memory, with the data being buffered in particular before thisoperation, and/or the data content of an external memory or acorrespondingly assessable information about the memory content of thememory, in whole or in part, is copied in real time into a memory of theembedded system, with the data being buffered in particular before thisoperation.
 35. The method of claim 34, wherein the external memory isused to transmit data for typical debugging applications.
 36. The methodof claim 35, wherein only the data needed for debugging is transferredto the external memory in the event of access operations of the CPU to37. The method of claim 34, wherein at least the write access operationsor the read access operations of the CPU are logged by means of a bufferstore.
 38. The method of claim 37, wherein information about the writeaccess operations is written without additional CPU commands into thebuffer store or directly into the communication module, and theinformation about the read access operations is written into the bufferstore with active assistance of the CPU.
 39. The method of claim 33,wherein a mode of the embedded system is provided in which all writeand/or read access operations of the CPU are rerouted to thecommunication module.
 40. The method of claim 33, wherein a mode of theembedded system is provided in which only either the write accessoperations or the read access operations of the CPU are rerouted to thecommunication module, and the other access operations of the CPU to thememory are logged actively by the CPU into the external memory.